Many digital systems have multiple clock domains. Thus, when signals move from one clock domain to another, they must be synchronized to avoid metastability and synchronization failure. If the two clocks have fixed frequencies, the phase relationship between the two clocks is periodic, at the beat frequency of the two clocks. By taking advantage of this periodic phase relationship, a periodic synchronizer can be simpler, have lower latency, and a lower probability of failure than a synchronizer that has to handle crossing clock domains where at least one of the clocks operates at a variable frequency.
When at least one of the clocks operates at a variable frequency, the design of the synchronizer is more complicated. Typically, signals passing between clock domains are synchronized with a periodic clock using asynchronous first-in-first outs (FIFOs). A significant area overhead is incurred for the FIFO memory. The FIFOs also add several cycles of delay as the Gray-coded input and output pointers of the FIFO must be synchronized through multiple flip-flops to reliably transmit the signals across clock domains.
There is thus a need for addressing these and/or other issues associated with the prior art.